1. Field of the Invention
This invention relates to a semiconductor integrated circuit test system. More specifically this invention relates to a semiconductor memory test device and a test method of a semiconductor memory device.
2. Description of the Prior Art
Recently, with the increase in the number of bits of a semiconductor memory device, a semiconductor memory device with a data width of 16 or 32 bits has been developed. The number of pins installed in a memory tester for monitoring data bits of a semiconductor memory device need to be increased with the expansion of a data width of the semiconductor memory device, so that if the data width of a semiconductor memory should expand, for example, from 4 to 32 bits, the number of semiconductor memory devices which can simultaneously be tested on a memory tester may decrease down to 1/8 in the worst case due to the restriction of the total pin counts installed in the memory tester.
For solving the above-mentioned problem, a parallel test technique implemented in a memory chip is widely employed. For example, with a technique disclosed on pp. 149-163 of NIKKEI ELECTRONICS Apr. 6, 1987, No. 418, a memory is internally divided into four blocks such that in testing the memory, the same data is written into each block and "1" is outputted if all data read from the blocks coincide, while "0" is outputted if they do not coincide.
FIG. 5 illustrates a block diagram of a prior art example of a parallel test technique for testing a semiconductor memory. Referring to FIG. 5, the same data is written into the memory blocks 502 to 505 and bit data outputted from the memory blocks 502 to 505 are inputted to a coincidence detection circuit 506 to be checked whether they coincide with each other.
According to the above constitution, even with the data width of a semiconductor memory increasing to 16 bits, or further up to 32 bits, it is enough to monitor only one-bit output signal from a coincidence detection circuit 506 for detecting a coincidence of bit data from memory blocks, so that the number of memories which can simultaneously be tested on a memory tester may be increased without being restricted by pin counts for monitoring data in a memory tester.
Recently, such a memory corresponding to the increase in an access speed, is used in practice as that comprising serial registers which read a plurality of data from memory blocks in parallel and outputs the data through the serial registers from output terminals of the memory chip at a high speed. The above-mentioned parallel test may also be applied for testing such a special memory.
Referring to FIG. 6, a conventional technique for testing a memory comprising serial registers is now explained. As shown in FIG. 6, in case of 4-bit parallel test, data read from memory blocks 602, 603, 604 and 605 every four bits in parallel is fed to serial registers 612, 613, 614 and 615 respectively and thereafter by setting a control signal b to "H" level, and supplying a clock signal c, data is read from a serial output terminal of the serial registers and compared by a coincidence detection circuit 607 from which "1" is outputted if all data coincide while "0" is outputted if they do not coincide.
FIG. 7(A) illustrates a circuit structure of the coincidence detection circuit 607 in FIG. 6. Referring to FIG. 7(A), the coincidence detection circuit 607 is composed of three 2-input exclusive NOR (XNOR) circuits and an AND gate such that an output h is set to "1" only if four inputs a0, b0, c0 and d0 are of the same logical value. FIG. 7(B) illustrates a circuit structure of the 2-input XNOR circuit at a transistor level. Referring to FIG. 7(B), when both inputs 7a and 7b are at "H" or "L" level, an output 7c comes to "H" level.
The memory shown in FIG. 6 may be reconfigured so as to compare 16 bits data read out of the memory blocks, that is, 4 bits.times.4 (memory blocks), without going through the serial registers, however, in such a case, the circuit size of a coincidence detection circuit increases. Therefore, the constitution shown in FIG. 6 is generally used.
As described above, the conventional technique for testing a semiconductor memory suffers from the drawback that the circuit size of the coincidence detection circuit increases as the number of blocks to be divided increases and the number of wires employed for interconnecting memory blocks also increases for outputting a comparison result between memory blocks as one bit data indicating a status of coincidence or non-coincidence.
More specifically, as shown in FIG. 8, when the number of memory blocks and the number of serial registers increases from 4 (see FIG. 8(A) to FIG. 8(B)), the number of XNOR gates to be operated as coincidence detection circuits increases by 4 and resultingly the number of 3-input AND gates increases by 2 in order to obtain the logical product of the comparison results between blocks, as a result of which, the number of wires also increases.